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verilog-hdl
- 本设计是以四路抢答为基本概念。从实际应用出发,利用电子设计自动化( EDA)技术,用可编程逻辑器件设计具有扩充功能的抢答器。它以Verilog HDL硬件描述语言作为平台，结合动手实验而完成的-The design is based on four basic concepts answer. From the practical application, the use of electronic design automation (EDA) technology, using a prog
Verilog.HDL
- <精通Verilog.HDL语言编程_源码>-< Proficient Verilog.HDL source programming language _>
Verilog.HDL
- 精通Verilog.HDL语言编程_源码，对初学者来说很好的值得借鉴-Proficient Verilog.HDL language programming _ source, good for beginners should learn
Verilog-HDL-washer
- 智能洗衣机控制器 基于verilog hdl状态机 具有多种功能切换-Intelligent washing machine controller verilog hdl-based state machine has multi-functional switch
Verilog-HDL--examples
- 王金明：《Verilog HDL 程序设计教程》书中的全部范例，pdf版本。-Wang Jinming: " Verilog HDL Programming Guide" all examples in the book, pdf version.
Verilog-HDL-basics-for-beginners
- Verilog HDL的基础知识,适合初学者阅读-Verilog HDL basics for beginners to read
Verilog-HDL-for-entering-Huawei
- Verilog HDL 华为入门教程 想去华为的可以学习下-Verilog HDL want Huawei Huawei introductory tutorial can learn under
Verilog-HDL
- 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha
verilog-hdl(VIA-COMPANY-DOCUMENTS)
- verilog hdl学习 威盛内部资料-verilog hdl language(VIA reference document)
Verilog-HDL-introduction
- 简单实用的Verilog HDL 入门教程-Verilog HDL introduction
vga显示实验及代码
- 里面有具体的关于VGA显示的实验说明及代码，基于verilog HDL语言，里面有三个实验及代码
seg7
- verilog HDL编写的FPGA定时器并用数码管显示(Verilog HDL prepared by the FPGA timer and digital display)
Verilog数字系统设计教程
- Verilog教程 数字系统设计 夏宇闻(Verilog Digital System Design)
cnt12
- 十二进制计数器，基于verilog HDL实现。(Twelve decimal counter)
mux_2to1_4to1_8to1
- design verilog hdl for mux 2to1, mux4to1, mux8to1
signed_add
- 有符号定点数加法运算代码，使用Verilog HDL语言实现(Code writing in Verilog HDL,to solve the problem about signed number calculation.)
xujiance
- 设计一个序检测电路，功能是检测出串行输入数据Data中的4位二进制序列1101（自左至右输入），当检测到该序列时，输出Out为1；没有检测到该序列时，输出输出Out为0，要求： （1）用状态机方法设计； （2）用Verilog HDL语言设计，用Modelsim软件做功能仿真。(A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data D
verilog add4
- 分两部分，基于verilog的四位和八位加法器设计，用synopsys的VCS仿真工具进行功能仿真，掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)
Verilog-HDL实用教程（张明）
- verilog教程，更加偏向工程化的verilog实用教程，有很多实际模块，推荐(Verilog tutorial, more biased toward the engineering of the Verilog practical tutorial, there are many practical modules, recommended)
Verilog典型电路设计_华为
- Verilog典型电路设计,学习价值较高。(Verilog typical circuit design, learning value is higher.)